FIELD OF THE INVENTION
The invention relates in general to the field of semiconductors, and specifically to a MOS transistor used as a selection transistor in a single-transistor memory cell, and to a production process.
MOS transistors form the basis of a large number of integrated circuits such as memory circuits or logic circuits. The growth in the integration density of integrated circuits requires that the gate length of the transistors be continually reduced. The gate length is the distance between the conductive regions of the MOS transistor, namely, the source and the drain. It is known in the prior art to provide the gate with nitride encapsulation. In particular, it is known to form the customary insulating spacers on the gate side walls from nitride in order to minimize the spacer thickness without detrimentally influencing the insulating effect. It is known that nitride spacers or a nitride etching stop layer on a top and a side gate insulation made of oxide, for example, can be used to produce a self-aligned contact with the source and the drain, in which the top and side gate insulation is not etched or attacked, or is etched or attacked only minimally.
The reduction in the gate length leads to increasing field strengths and hence to problems, particularly with the breakdown voltage and reliability of the transistor because of leakage currents.
Such a transistor having nitride encapsulation can be used, by way of example, as a selection transistor in a DRAM memory cell. There are a multiplicity of cell designs for DRAM memories. One example is a so-called trench cell with a surface strap. In this cell design, the storage capacitor is produced in a trench in the semiconductor substrate, and the storage electrode is configured in the trench. The capacitor dielectric covers the trench wall. The selection transistor is configured adjacent the trench. The electrical connection between the storage electrode and a doped region of the selection transistor is produced with a polysilicon structure (surface strap) that is configured on the substrate surface and overlaps the trench filler and the doped region.
With single-transistor memory cells, particularly DRAM memory cells, a leakage current results, in particular a current caused by the so-called GIDL effect (GIDL =Gate Induced Drain Leakage). A GIDL current causes the information retention time of the cell to be reduced. This applies particularly to the side of the selection transistor connected to the storage capacitor. Therefore, the GIDL current needs to be minimized.
One measure for reducing the GIDL effect is to reduce the diffusion of ion implantations below the gate. This is done by reducing the high-temperature steps after the critical implantations (implantation of source and drain). The associated additional process limitations are a considerable disadvantage. Another possibility is a complex, complete redesign of the module. However, both measures have limited effectiveness.